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july 1996 product highlights low cost replacement for discrete switchers ? 20 to 50 fewer components - cuts cost, increases reliability ? source-connected tab and controlled mosfet turn-on reduce emi and emi filter costs ? allows for a 50% smaller and lighter solution ? cost competitive with linears above 5 w up to 90% efficiency in flyback topology ? built-in start-up and current limit reduce dc losses ? low capacitance 700 v mosfet cuts ac losses ? cmos controller/gate driver consumes only 6 mw ? 70% maximum duty cycle minimizes conduction losses simplifies design - reduces time to market ? supported by many reference design boards ? integrated pwm controller and 700 v mosfet in a industry standard three pin to-220 package ? only one external capacitor needed for compensation, bypass and start-up/auto-restart functions system level fault protection features ? auto-restart and cycle by cycle current limiting functions handle both primary and secondary faults ? on-chip latching thermal shutdown protects the entire system against overload highly versatile ? implements buck, boost, flyback or forward topology ? easily interfaces with both opto and primary feedback ? supports continuous or discontinuous mode of operation description the topswitch family implements, with only three pins, all functions necessary for an off-line switched mode control system: high voltage n-channel power mosfet with controlled turn-on gate driver, voltage mode pwm controller with integrated 100 khz oscillator, high voltage start-up bias circuit, bandgap derived reference, bias shunt regulator/error amplifier for loop compensation and fault protection circuitry. compared to discrete mosfet and controller or self oscillating (rcc) switching converter solutions, a topswitch integrated circuit can reduce total cost, component count, size, weight and at the same time increase efficiency and system reliability. these ? pi-1703-112995 ac in drain source control topswitch figure 1. typical application. top200-4/14 topswitch family three-terminal off-line pwm switch devices are intended for 100/110/230 vac off-line power supply applications in the 0 to 100 w (0 to 50 w universal) range and 230/277 vac off-line power factor correction (pfc) applications in the 0 to 150 w range. top200yai* 0-25 w 0-12 w 0-25 w top201yai* 20-45 w 10-22 w 20-50 w top202yai* 30-60 w 15-30 w 30-75 w top203yai* 40-70 w 20-35 w 50-100 w top214yai* 50-85 w 25-42 w 60-125 w top204yai* 60-100 w 30-50 w 75-150 w order part number 230 vac or 110 vac w/doubler flyback 85-265 vac pfc/ boost 230/277 vac output power range topswitch selection guide ? * package outline: y03a
top200-4/14 d 7/96 2 figure 2. functional block diagram. pin functional description drain pin: output mosfet drain connection. provides internal bias current during start-up operation via an internal switched high- voltage current source. internal current sense point. control pin: error amplifier and feedback current input pin for duty cycle control. internal shunt regulator connection to provide internal bias current during normal operation. trigger input for latching shutdown. it is also used as the supply bypass and auto-restart/ compensation capacitor connection point. source pin: output mosfet source connection. primary-side circuit common, power return, and reference point. pi-1065a-110194 control drain source (tab) to-220/3 (yo3a) figure 3. pin configuration. pi-1746-011796 shutdown/ auto-restart pwm comparator clock saw oscillator controlled turn-on gate driver internal supply 5.7 v 4.7 v source s r q q d max - + control - + 5.7 v i fb r e z c v c minimum on-time delay + - v i limit leading edge blanking power-up reset r s q q ? 8 0 1 thermal shutdown externally triggered shutdown shunt regulator/ error amplifier + - drain
d 7/96 top200-4/14 3 topswitch family functional description topswitch is a self biased and protected linear control current-to-duty cycle converter with an open drain output. high efficiency is achieved through the use of cmos and integration of the maximum number of functions possible. cmos significantly reduces bias currents as compared to bipolar or discrete solutions. integration eliminates external power resistors used for current sensing and/or supplying initial start-up bias current. during normal operation, the internal output mosfet duty cycle linearly decreases with increasing control pin current as shown in figure 4. to implement all the required control, bias, and protection functions, the drain and control pins each perform several functions as described below. refer to figure 2 for a block diagram and figure 6 for timing and voltage waveforms of the topswitch integrated circuit. control voltage supply control pin voltage v c is the supply or bias voltage for the controller and driver circuitry. an external bypass capacitor closely connected between the control and source pins is required to supply the gate drive current. the total amount of capacitance connected to this pin (c t ) also sets the auto-restart timing as well as control loop compensation. v c is regulated in either of two modes of operation. hysteretic regulation is used for initial start-up and overload operation. shunt regulation is used to separate the duty cycle error signal from the control circuit supply current. during start-up, v c current is supplied from a high-voltage switched current source connected internally between the drain and control pins. the current source provides sufficient current to supply the control circuitry as well as charge the total external capacitance (c t ). pi-1691-112895 d max d min i cd1 duty cycle (%) i c (ma) 2.5 6.5 45 slope = pwm gain -16%/ma i b auto-restart figure 4. relationship of duty cycle to control pin current. figure 5. start-up waveforms for (a) normal operation and (b) auto-restart. drain 0 v in v c 0 4.7 v 5.7 v 8 cycles 95% 5% off switching switching off i c charging c t i cd1 discharging c t i cd2 discharging c t i c charging c t off pi-1124a-060694 drain 0 v in v c 0 4.7 v 5.7 v off switching (b) (a) c t is the total external capacitance connected to the control pin
top200-4/14 d 7/96 4 the first time v c reaches the upper threshold, the high-voltage current source is turned off and the pwm modulator and output transistor are activated, as shown in figure 5(a). during normal operation (when the output voltage is regulated) feedback control current supplies the v c supply current. the shunt regulator keeps v c at typically 5.7 v by shunting control pin feedback current exceeding the required dc supply current through the pwm error signal sense resistor r e . the low dynamic impedance of this pin (z c ) sets the gain of the error amplifier when used in a primary feedback configuration. the dynamic impedance of the control pin together with the external resistance and capacitance determines the control loop compensation of the power system. if the control pin external capacitance (c t ) should discharge to the lower threshold, then the output mosfet is turned off and the control circuit is placed in a low-current standby mode. the high-voltage current source is turned on and charges the external capacitance again. charging current is shown with a negative polarity and discharging current is shown with a positive polarity in figure 6. the hysteretic auto-restart comparator keeps v c within a window of typically 4.7 to 5.7 v by turning the high-voltage current source on and off as shown in figure 5(b). the auto-restart circuit has a divide- by-8 counter which prevents the output mosfet from turning on again until eight discharge-charge cycles have elapsed. the counter effectively limits topswitch power dissipation by reducing the auto-restart duty cycle to typically 5%. auto-restart continues to cycle until output voltage regulation is again achieved. bandgap reference all critical topswitch internal voltages are derived from a temperature- compensated bandgap reference. this reference is also used to generate a temperature-compensated current source which is trimmed to accurately set the oscillator frequency and mosfet gate drive current. oscillator the internal oscillator linearly charges and discharges the internal capacitance between two voltage levels to create a sawtooth waveform for the pulse width modulator. the oscillator sets the pulse width modulator/current limit latch at the beginning of each cycle. the nominal frequency of 100 khz was chosen to minimize emi and maximize efficiency in power supply applications. trimming of the current reference improves oscillator frequency accuracy. pulse width modulator the pulse width modulator implements a voltage-mode control loop by driving the output mosfet with a duty cycle inversely proportional to the current flowing into the control pin. the error signal across r e is filtered by an rc network with a typical corner frequency of 7 khz to reduce the effect of switching noise. the filtered error signal is compared with the internal oscillator sawtooth waveform to generate the duty cycle waveform. as the control current increases, the duty cycle decreases. a clock signal from the oscillator sets a latch which turns on the output mosfet. the pulse width modulator resets the latch, turning off the output mosfet. the maximum duty cycle is set by the symmetry of the internal oscillator. the modulator has a minimum on-time to keep the current consumption of the topswitch independent of the error signal. note that a minimum current must be driven into the control pin before the duty cycle begins to change. gate driver the gate driver is designed to turn the output mosfet on at a controlled rate to minimize common-mode emi. the gate drive current is trimmed for improved accuracy. error amplifier the shunt regulator can also perform the function of an error amplifier in primary feedback applications. the shunt regulator voltage is accurately derived from the temperature compensated bandgap reference. the gain of the error amplifier is set by the control pin dynamic impedance. the control pin clamps external circuit signals to the v c voltage level. the control pin current in excess of the supply current is separated by the shunt regulator and flows through r e as the error signal. cycle-by-cycle current limit the cycle by cycle peak drain current limit circuit uses the output mosfet on-resistance as a sense resistor. a current limit comparator compares the output mosfet on-state drain-source voltage, v ds(on), with a threshold voltage. high drain current causes v ds(on) to exceed the threshold voltage and turns the output mosfet off until the start of the next clock cycle. the current limit comparator threshold voltage is temperature compensated to minimize variation of the effective peak current limit due to temperature related changes in output mosfet r ds(on) . the leading edge blanking circuit inhibits the current limit comparator for a short time after the output mosfet is turned on. the leading edge blanking time has been set so that current spikes caused by primary-side capacitances and secondary-side rectifier reverse recovery time will not cause premature termination of the switching pulse. topswitch family functional description (cont.)
d 7/96 top200-4/14 5 pi-1119-110194 v in v out 0 i out 0 1 2 1 4 3 drain 0 v in v c 0 ?? ?? 12 12 81 0 i c ?? ?? 12 8 812 81 v c(reset) 45 ma shutdown/auto-restart to minimize topswitch power dissipation, the shutdown/auto-restart circuit turns the power supply on and off at a duty cycle of typically 5% if an out of regulation condition persists. loss of regulation interrupts the external current into the control pin. v c regulation changes from shunt mode to the hysteretic auto-restart mode described above. when the fault condition is removed, the power supply output becomes regulated, v c regulation returns to shunt mode, and normal operation of the power supply resumes. latching shutdown the output overvoltage protection latch is activated by a high-current pulse into the control pin. when set, the latch turns off the topswitch output. activating the power-up reset circuit by removing and restoring input power, or momentarily pulling the control pin below the power-up reset threshold resets the latch and allows topswitch to resume normal power supply operation. v c is regulated in hysteretic mode when the power supply is latched off. overtemperature protection temperature protection is provided by a precision analog circuit that turns the output mosfet off when the junction temperature exceeds the thermal shutdown temperature (typically 145 c). activating the power-up reset circuit by removing and restoring input power or momentarily pulling the control pin below the power-up reset threshold resets the latch and allows topswitch to resume normal power supply operation. v c is regulated in hysteretic mode when the power supply is latched off. high-voltage bias current source this current source biases topswitch from the drain pin and charges the control pin external capacitance (c t ) during start-up or hysteretic operation. hysteretic operation occurs during auto-restart and latched shutdown. the current source is switched on and off with an effective duty cycle of approximately 35%. this duty cycle is determined by the ratio of control pin charge (i c ) and discharge currents (i cd1 and i cd2 ). this current source is turned off during normal operation when the output mosfet is switching. figure 6. typical waveforms for (1) normal operation, (2) auto-restart, (3) latching shutdown, and (4) power down reset.
top200-4/14 d 7/96 6 general circuit operation primary feedback regulation the circuit shown in figure 7 is a simple 5 v, 5 w bias supply using the top200. this universal input flyback power supply employs primary-side regulation from a transformer bias winding. this approach is best for low-cost applications requiring isolation and operation within a narrow range of load variation. line and load regulation of 5% or better can be achieved from 10% to 100% of rated load. voltage feedback is obtained from the transformer (t1) bias winding, which eliminates the need for optocoupler and secondary-referenced error amplifier. high-voltage dc is applied to the primary winding of t1. the other side of the transformer primary is driven by figure 7. schematic diagram of a minimum parts count 5 v, 5 w bias supply utilizing the top200. the integrated high-voltage mosfet transistor within the top200 (u1). the circuit operates at a switching frequency of 100 khz, set by the internal oscillator of the top200. the clamp circuit implemented by vr1 and d1 limits the leading-edge voltage spike caused by transformer leakage inductance to a safe value. the 5 v power secondary winding is rectified and filtered by d2, c2, c3, and l1 to create the 5 v output voltage. the output of the t1 bias winding is rectified and filtered by d3, r1, and c5. the voltage across c5 is regulated by u1, and is determined by the 5.7 v internal shunt regulator at the control pin of u1. when the rectified bias voltage on c5 begins to exceed the shunt regulator voltage, current will flow into the control pin. increasing control pin current decreases the duty cycle until a stable operating point is reached. the output voltage is proportional to the bias voltage by the turns ratio of the output to bias windings. c5 is used to bypass the control pin. c5 also provides loop compensation for the power supply by shunting ac currents around the control pin dynamic impedance, and also determines the auto-restart frequency during start- up and auto-restart conditions. see dn- 8 for more information regarding the use of the top200 in bias supplies. pi-1749-012296 5 v rtn c5 47 m f u1 top200yai d2 1n5822 d3 1n4148 l1 (bead) c2 330 m f 25 v c3 150 m f 25 v t1 d1 uf4005 dc input vr1 1n4764 r1 22 w circuit performance: load regulation - ?% (10% to 100%) line regulation - ?.5% 95 to 370 v dc ripple voltage ?5 mv drain source control
d 7/96 top200-4/14 7 simple optocoupler feedback the circuit shown in figure 8 is a 7.5 v, 15 w secondary regulated flyback power supply using the top202 that will operate from 85 to 265 vac input voltage. improved output voltage accuracy and regulation over the circuit of figure 7 is achieved by using an optocoupler and secondary referenced zener diode. the general operation of the power stage of this circuit is the same as that described for figure 7. the input voltage is rectified and filtered by br1 and c1. l2, c6 and c7 reduce conducted emission currents. the bias winding is rectified and filtered by d3 and c4 to create a typical 11 v bias voltage. zener diode (vr2) voltage together with the forward voltage of the led in the optocoupler u2 determine the output voltage. r1, the optocoupler current transfer ratio, and the topswitch control current to duty cycle transfer function set the dc control loop gain. c5 together with the control pin dynamic impedance and capacitor esr establish a control loop pole-zero pair. c5 also determines the auto-restart frequency and filters internal gate drive switching currents. r2 and vr2 provide minimum current loading when output current is low. see dn-11 for more information regarding the use of the top202 in a low-cost, 15 w universal power supply. accurate optocoupler feedback the circuit shown in figure 9 is a highly accurate, 15 v, 30 w secondary- regulated flyback power supply that will operate from 85 to 265 vac input voltage. a tl431 shunt regulator directly senses and accurately regulates the output voltage. the effective output voltage can be fine tuned by adjusting the resistor divider formed by r4 and r5. other output voltages are possible by adjusting the transformer turns ratios as well as the divider ratio. the general operation of the input and power stages of this circuit are the same as that described for figures 7 and 8. r3 and c5 tailor frequency response. the tl431 (u2) regulates the output voltage by controlling optocoupler led current (and topswitch duty cycle) to maintain an average voltage of 2.5 v at the tl431 input pin. divider r4 and r5 determine the actual output voltage. c9 rolls off the high frequency gain of the tl431 for stable operation. r1 limits optocoupler led current and determines high frequency loop gain. for more information, refer to application note an-14. figure 8. schematic diagram of a 15 w universal input power supply utilizing the top202 and simple optocoupler feedback. pi-1695-112895 7.5 v rtn c5 47 m f d2 ug8bt d3 1n4148 r2 68 w vr2 1n5234b 6.2 v c3 120 m f 25 v t1 d1 uf4005 c2 680 m f 25 v vr1 p6ke150 circuit performance: line regulation - ?.5% (85-265 vac) load regulation - ?% (10 -100%) ripple voltage ?50 mv meets cispr-22 class b br1 400 v c1 33 m f 400 v r1 39 w u2 nec2501 u1 top202yai drain source control c4 0.1 m f c7 1 nf y1 l1 3.3 m h f1 3.15 a j1 c6 0.1 m f l2 22 mh l n st202a reference design board
top200-4/14 d 7/96 8 figure 10. schematic diagram of a 65 w 230 vac input boost power factor correction circuit utilizing the top202. figure 9. schematic diagram of a 30 w universal input power supply utilizing the top204 and accurate optocoupler feedback. pi-1696-112895 15 v rtn br1 400 v c1 47 m f 400 v c5 47 m f c4 0.1 m f u1 top204yai r3 6.2 w r2 200 w 1/2 w d2 mur610ct d3 1n4148 c2 1000 m f 35 v t1 d1 byv26c c7 1 nf y1 drain source control c3 120 m f 25 v u2 nec2501 u3 tl431 r4 49.9 k w r5 10 k w c9 0.1 m f r1 510 w vr1 p6ke200 l1 3.3 m h f1 3.15 a j1 c6 0.1 m f l2 33 mh l n circuit performance: line regulation - ?.2% (85-265 vac) load regulation - ?.2% (10-100%) ripple voltage ?50 mv meets cispr-22 class b st204a reference design board pi-1750-012296 v o rtn d1 mur460 br1 400 v r1 200 k w r2 200 w r10 6.8 k w r3 3 k w vr1 in5386b vr2 in5386b d2 1n4935 c1 220 nf 400 v c4 47 m f c2 4.7 m f c3 220 m f l1 500 m h emi filter ac in u1 top202yai drain source control typical performance: power factor = 0.98 thd = 8%
d 7/96 top200-4/14 9 boost pfc pre-regulator topswitch can also be used as a fixed frequency, discontinuous mode boost pre-regulator to improve power factor and reduce total harmonic distortion (thd) for applications such as power supplies and electronic ballasts. the circuit shown in figure 10 operates from 230 vac and delivers 65 w at 410 vdc with typical power factor over 0.98 and thd of 8%. bridge rectifier br1 full wave rectifies the ac input voltage. l1, d1, c4, and topswitch make up the boost power stage. d2 prevents reverse current through the topswitch body diode due to ringing voltages generated general circuit operation (cont.) when power is first applied, c3 charges to typically 5.7 volts before topswitch starts. c3 then provides topswitch bias current until the output voltage becomes regulated. when the output voltage becomes regulated, series connected zener diodes vr1 and vr2 begin to conduct, drive current into the topswitch control pin, and directly control the duty cycle. c3 together with r3 perform low pass filtering on the feedback signal to prevent output line frequency ripple voltage from varying the duty cycle. for more information, refer to design note dn-7. keep the source pin length very short. use a kelvin connection to the source pin for the control pin bypass capacitor. use single point grounding techniques at the source pin as shown in figure 11. minimize peak voltage and ringing on the drain voltage at turn-off. use a zener or tvs zener diode to clamp the drain voltage. do not plug the topswitch device into a hot ic socket during test. external control pin capacitance may deliver a surge current sufficient to trigger the shutdown latch which turns the topswitch off. under some conditions, externally provided bias or supply current driven into the control pin can hold the topswitch in one of the 8 auto-restart cycles indefinitely and prevent starting. shorting the control pin to the source pin will reset the topswitch . to avoid this problem when doing bench evaluations, it is recommended that the v c power supply be turned on before the drain voltage is applied. control pin currents during auto- restart operation are much lower at low input voltages (< 20 v) which increases the auto-restart cycle period (see the i c vs. drain voltage characteristic curve). short interruptions of ac power may cause topswitch to enter the 8-count auto-restart cycle before starting again. this is because the input energy storage capacitors are not completely discharged and the control pin capacitance has not discharged below the pin internal power-up reset voltage. in some cases, minimum loading may be necessary to keep a lightly loaded or unloaded output voltage within the desired range due to the minimum on- time. for additional applications information regarding the topswitch family, refer to an-14. key application issues figure 11. recommended topswitch layout. pi-1240-110194 pc board kelvin-connected bypass capacitor and/or compensation network bias/feedback input bias/feedback return high-voltage return bend drain pin forward if needed for creepage drain source control do not bend source pin keep it short high voltage return bias/feedback return bypass capacitor d s c top view bias/feedback input by the boost inductance and parasitic capacitance. r1 generates a pre- compensation current proportional to the instantaneous rectified ac input voltage which directly varies the duty cycle. c2 filters high frequency switching currents while having no filtering effect on the line frequency pre- compensation current. r2 decouples the pre-compensation current from the large filter capacitor c3 to prevent an averaging effect which would increase total harmonic distortion. c1 filters high frequency noise currents which could cause errors in the pre- compensation current.
top200-4/14 d 7/96 10 absolute maximum ratings (1) drain voltage ............................................ -0.3 to 700 v control voltage ..................................... - 0.3 v to 9 v storage temperature ...................................... -65 to 125 c operating junction temperature (2) ................. -40 to 150 c lead temperature (3) ................................................. 260 c thermal impedance ( q ja ) ...................................... 70 c/w thermal impedance ( q jc ) (4) .................................... 2 c/w 1. unless noted, all voltages referenced to source, t a = 25 c. 2. normally limited by internal circuitry. 3. 1/16" from case for 5 seconds. 4. measured at tab closest to plastic interface. i c = 4 ma, t j = 25?c i c = i cd1 + 0.5 ma, see figure 12 i c = 10 ma, top200/1/2 see figure 12 top203/4/14 i c = 4 ma, t j = 25?c see figure 4 see note 1 see figure 4 i c = 4 ma, t j = 25?c see figure 13 v c = 0 v t j = 25?c v c = 5 v see note 1 s1 open 90 100 110 64 67 70 1.0 1.8 3.0 1.0 2.0 3.5 -11 -16 -21 -0.05 1.5 2.5 4 10 15 22 0.18 -2.4 -1.9 -1.2 -2 -1.5 -0.8 0.4 5.7 f osc dc max dc min i b z c i c v c(ar) control functions output frequency maximum duty cycle minimum duty cycle pwm gain pwm gain temperature drift external bias current dynamic impedance dynamic impedance temperature drift control pin charging current charging current temperature drift auto-restart threshold voltage khz % % %/ma %/ma/?c ma w %/?c ma %/?c v shutdown/auto-restart conditions (unless otherwise specified) parameter symbol see figure 14 units source = 0 v t j = -40 to 125 c min typ max
d 7/96 top200-4/14 11 4.7 0.6 1.0 58 1.2 0.415 0.585 0.830 1.17 1.25 1.75 1.50 2.10 1.88 2.63 2.25 3.15 150 100 125 145 25 45 75 2.0 3.3 4.2 s1 open s1 open s1 open s1 open top200 di/dt = 80 ma/ m s, t j = 25?c top201 di/dt = 170 ma/ m s, t j = 25?c top202 di/dt = 250 ma/ m s, t j = 25?c top203 di/dt = 330 ma/ m s, t j = 25?c top214 di/dt = 420 ma/ m s, t j = 25?c top204 di/dt = 500 ma/ m s, t j = 25?c i c = 4 ma i c = 4 ma i c = 4 ma see figure 13 s2 open i limit t leb t ild i sd v c(reset) v v % hz a ns ns c ma v shutdown/auto-restart (cont.) uv lockout threshold voltage auto-restart hysteresis voltage auto-restart duty cycle auto-restart frequency self-protection current limit leading edge blanking time current limit delay thermal shutdown temperature latched shutdown trigger current power-up reset threshold voltage circuit protection conditions (unless otherwise specified) parameter symbol see figure 14 units source = 0 v t j = -40 to 125 c min typ max
top200-4/14 d 7/96 12 top200 t j = 25 c i d = 50 ma t j = 100 c top201 t j = 25 c i d = 100 ma t j = 100 c top202 t j = 25 c i d = 150 ma t j = 100 c top203 t j = 25 c i d = 200 ma t j = 100 c top214 t j = 25 c i d = 250 ma t j = 100 c top204 t j = 25 c i d = 300 ma t j = 100 c device in latched shutdown i c = 4 ma, v ds = 560 v, t a = 125 c device in latched shutdown i c = 4 ma, i d = 500 m a, t a = 25 c measured with figure 8 schematic measured with figure 8 schematic see note 2 i c = 4 ma output top200/1/2 mosfet enabled top203/4/14 output mosfet disabled r ds(on) i dss bv dss t r t f v c(shunt) i cd1 i cd2 15.6 18.0 25.7 29.7 7.8 9.0 12.9 14.9 5.2 6.0 8.6 9.9 3.9 4.5 6.4 7.5 3.1 3.6 5.2 6.0 2.6 3.0 4.3 5.0 500 700 100 50 36 5.5 5.8 6.1 50 0.6 1.2 1.6 0.7 1.4 1.8 0.5 0.8 1.1 on-state resistance off-state current breakdown voltage rise time fall time drain supply voltage shunt regulator voltage shunt regulator temperature drift control supply/ discharge current w m a v ns ns v v ppm/?c ma output supply conditions (unless otherwise specified) parameter symbol see figure 14 units source = 0 v t j = -40 to 125 c min typ max
d 7/96 top200-4/14 13 notes: 1. for specifications with negative values, a negative temperature coefficient corresponds to an increase in magnitude with increasing temperature, and a positive temperature coefficient corresponds to a decrease in magnitude with increasing temperature. 2. it is possible to start up and operate topswitch at drain voltages well below 36 v. however, the control pin charging current is reduced, which affects start-up time and auto-restart frequency and duty cycle. refer to the characteristic graph on control pin charge current (i c ) vs. drain voltage for low voltage operation characteristics. pi-1126-041994 0.1 m f 47 m f 0-50 v 40 v topswitch 470 w 5 w s2 s1 470 w drain source control note: this test circuit is not applicable for current limit or output characteristic measurements. figure 14. topswitch general test circuit. pi-1215-091794 drain voltage hv 0 v 90% 10% 90% t 2 t 1 dc = t 1 t 2 figure 12. topswitch duty cycle measurement. figure 13. topswitch control pin i-v characteristic. 120 100 80 40 20 60 0 0246810 control pin voltage (v) control pin current (ma) typical control pin i-v characteristic pi-1216-091794 latched shutdown trigger current (45 ma) 1 slope dynamic impedance =
top200-4/14 d 7/96 14 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) current limit vs. temperature pi-1125-041494 current limit (normalized to 25 c) 2 1.2 1.6 0 0 204060 80100 drain voltage (v) control pin charging current (ma) i c vs. drain voltage pi-1145-103194 0.4 0.8 v c = 5 v the control pin voltage will be oscillating at a low frequency from 4.7 to 5.7 v and the drain is turned on every eighth cycle of the control pin oscillation. if the control pin power supply is turned on while in this auto-restart mode, there is only a 12.5% chance that the control pin oscillation will be in the correct state (drain active state) so the following precautions should be followed when testing topswitch by itself outside of a power supply. the schematic shown in figure 14 is suggested for laboratory testing of topswitch . when the drain supply is turned on, the part will be in the auto-restart mode. bench test precautions for evaluation of electrical characteristics 1.1 1.0 0.9 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) breakdown voltage (v) (normalized to 25 c) breakdown vs. temperature pi-176b-051391 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) frequency vs. temperature pi-1123a-060794 output frequency (normalized to 25 c) that the continuous drain voltage waveform may be observed. it is recommended that the v c power supply be turned on first and the drain power supply second if continuous drain voltage waveforms are to be observed. the 12.5% chance of being in the correct state is due to the 8:1 counter. typical performance characteristics
d 7/96 top200-4/14 15 typical performance characteristics (cont.) 1000 10 0 400 200 600 drain voltage (v) drain capacitance (pf) c oss vs. drain voltage 100 pi-1223-110294 scaling factors: top204 1.00 top214 0.83 top203 0.67 top202 0.50 top201 0.33 top200 0.17 3 0 0 246810 drain voltage (v) drain current (a) output characteristics pi-1748-012296 1 scaling factors: top204 1.00 top214 0.83 top203 0.67 top202 0.50 top201 0.33 top200 0.17 tcase=25?c tcase=100?c 2 500 300 400 100 200 0 0 200 400 600 drain voltage (v) power (mw) drain capacitance power pi-1222-102194 scaling factors: top204 1.00 top214 0.83 top203 0.67 top202 0.50 top201 0.33 top200 0.17
top200-4/14 d 7/96 16 japan power integrations, k.k. keihin-tatemono 1st bldg. 12-20 shin-yokohoma 2-chome, kohoku-ku yokohama-shi, kanagawa 222 japan phone: 81?(0)?45?471?1021 fax: 81?(0)?45?471?3717 asia & oceania for your nearest sales/rep office please contact customer service phone: 408?523?9265 fax: 408?523?9365 world headquarters power integrations, inc. 477 n. mathilda avenue sunnyvale, ca 94086 usa main: 408?523?9200 customer service: phone: 408?523?9265 fax: 408?523?9365 americas for your nearest sales/rep office please contact customer service phone: 408?523?9265 fax: 408?523?9365 power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it convey any license under its patent rights or the rights of others. pi logo and topswitch are registered trademarks of power integrations, inc. ?copyright 1994, power integrations, inc. 477 n. mathilda avenue, sunnyvale, ca 94086 applications hotline world wide 408?523?9260 applications fax americas 408?523?9361 europe/africa 44?(0)?1753?622?209 japan 81?(0)?45?471?3717 asia/oceania 408?523?9364 europe & africa power integrations (europe) ltd. mountbatten house fairacres windsor sl4 4le united kingdom phone: 44?(0)?1753?622?208 fax: 44?(0)?1753?622?209 b k f g c j l m e a d dim a b c d e f g h j k l m n o p pi-1848-050696 inches .460-.480 .400-.415 .236-.260 .240 - ref. .520-.560 .028-.038 .045-.055 .090-.110 .165-.185 .045-.055 .095-.115 .015-.020 .705-.715 .146-.156 .103-.113 mm 11.68-12.19 10.16-10.54 5.99-6.60 6.10 - ref. 13.21-14.22 .71-.97 1.14-1.40 2.29-2.79 4.19-4.70 1.14-1.40 2.41-2.92 .38-.51 17.91-18.16 3.71-3.96 2.62-2.87 h * leads and tab are solder plated n o p notes: 1. package dimensions conform to jedec specification to-220 ab for standard flange mounted, peripheral lead package; .100 inch lead spacing (plastic) 3 leads (issue j, march 1987) 2. controlling dimensions are inches. 3. pin numbers start with pin 1, and continue from left to right when viewed from the top. 4. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15 mm) on any side. 5. position of terminals to be measured at a position .25 (6.35 mm) from the body. 6. all terminals are solder plated. y03a plastic to-220/3

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